• Independently plan and implement layout for RF/Analog, mixed signal blocks and full chips using sub micron geometry technology, while adhering to specifications and guidelines set by design engineers.
  • Reading schematics, layout of circuits, and integration into a larger chip layout plan. 
  • Assist design engineering team with tapeout activities. 
  • Work closely with the design engineering team on a day-to-day basis to solve physical design issues. 
  • Ability to instruct, support, and lead layout activities. 
  • Ability to work efficiently as part of a team as well as independently. 
  • Global viewing from top level chip planning to low transistor level. 
  • Read and understand schematics with emphasis on identifying critical areas of design. 
  • Working knowledge of foundry design rules and application to maintain a layout within these constraints. 
  • Perform custom layout and verification of high performance Analog/RF IC products designed in BiCMOS/CMOS technologies. 
  • Strong background in Cadence/Mentor tools and environment. 
  • Independently identify, debug, and solve physical verification discrepancies in DRC, LVS, ANT,
  • DFM, Extraction, ESD and latchup check



TOWER-Jazz, SAMSUNG, TSMC28nm,TSMC40nm, TSMC65nm, TSMC90nm, TSMC13RF mixed signal, UMC110nm, GF180nm, GF130nm,MagnaChip, IBM7WL5LM, SBC18HA (TowerJazz).          




Cadence Virtuoso-XL Ver 6.1.6 Circuit/Layout Editor, Assura/PVS (DRC/LVS/ERC/ANT), Calibre (DRC/LVS/ERC/ANT), QRC
Unix/Linux environment. 

Analog Circuits:  Transmitter 6.25GHz, DAC/ADC, Sigma Delta 16bit, PLL 2.5GHz, BG, BB,
LVDS, Synthesizer.
RFIC Circuits: 60G circuits, VCO- 5GHz w-band, PLL80M/1.5G, RF poly phase, Mixers, Local oscillator, Transceiver (TX), Transmitter (RX) - 1.9/5.8G, Drivers, IO Pad cells and more.
Comment: All cells/blocks Consider latch up event, guard ring, Shielding, deep N-well, matching/symmetry, electro migration, antenna, differential pair and noise sensitivity and MD.