Independently plan and implement layout for RF/Analog, mixed signal blocks and full chips using sub micron geometry technology, while adhering to specifications and guidelines set by design engineers.
Reading schematics, layout of circuits, and integration into a larger chip layout plan.
Assist design engineering team with tapeout activities.
Work closely with the design engineering team on a day-to-day basis to solve physical design issues.
Ability to instruct, support, and lead layout activities.
Ability to work efficiently as part of a team as well as independently.
Global viewing from top level chip planning to low transistor level.
Read and understand schematics with emphasis on identifying critical areas of design.
Working knowledge of foundry design rules and application to maintain a layout within these constraints.
Perform custom layout and verification of high performance Analog/RF IC products designed in BiCMOS/CMOS technologies.
Strong background in Cadence/Mentor tools and environment.
Independently identify, debug, and solve physical verification discrepancies in DRC, LVS, ANT,
