YCell has a highly experienced CAD team with over 10 years of average experience in the industry with broad and deep knowledge of the semiconductor design and design flow. The team has an established track record of owning and delivering on-time and on-quality of cross-functional and complex projects.
We have experience in:
Support for analog/mixed-signal simulation and verification.
Full chip LVS, DRC and parasitic extraction run-sets and flow.
Expert in various Silicon FAB PDK – integration, Files manipulations, Modeling editing.
PDK compilation into CDN ENV – using “Cell Base” & “OSS” with I run models.
Analog layout automation.
Designed and developed large scale, high performance tools for VLSI design automation.
Programming Languages: C, C++, SKILL, Perl, UNIX/Linux c-shell, Tcl/Tk, Prolog, SQLplus, MySQL DataLayer, Cobol, ASP.NET and Visual Basic, SystemVerilog, awk, and Matlab.
Operating Systems: Linux, Windows.
Development tools: GNU toolchain (make, gcc, gdb), ups, MS Visual Studio, Rational Purify, Rational Quantify, Visio.
Technologies: STL, flex, yacc.
Version Control: SVN,CVS, synchronicity, ClioSoft (SOS), IC manage.